module systemAccess(reset,
 instPC, exceptions, busValid, busDestinyWrite, busDataWrite, busAdressWrite, interruption, jaCALLSiROBbuit, jaRETIiROBbuit, callSys, retSys, pcUp, typeCallSys, TLBAdress, interrOK, pc);

	input reset, jaCALLSiROBbuit, jaRETIiROBbuit, interruption, busValid, interrOK;
	input[3:0] busDestinyWrite;
	input[15:0] instPC, exceptions, busAdressWrite, pc;
	input[31:0] busDataWrite;

	output callSys, retSys;
	output[15:0] pcUp, typeCallSys, TLBAdress;
	
	reg readed, callSys, retSys;
	reg[15:0] readedPcUp, pcUp, typeCallSys, TLBAdress;
	
	always @ (*)
	begin
	
		if (reset) begin
		
			readed = 0;
			callSys = 0;
			retSys = 0;
			readedPcUp = 0;
			pcUp = 0;
			typeCallSys = 0;
			TLBAdress = 0;
			
		end
		else if (jaRETIiROBbuit) begin
		
			callSys = 0;
			retSys = 1;
		
		end
		else if (jaCALLSiROBbuit) begin
		
			callSys = 1;
			retSys = 0;
			typeCallSys = 16'b0100000000000000;
			
			if (readed) begin
				pcUp = readedPcUp;
				readed = 0;
			end
			else begin
				pcUp = instPC + 2;
			end
		
		end
		else if ((exceptions != 0) && (busValid == 1)) begin
		
			callSys = 1;
			retSys = 0;
			
			if (exceptions[4] == 1) begin
				typeCallSys = 16'b0000000000010000;
				pcUp = instPC;
				TLBAdress = instPC;
			end
			else if (exceptions[0] == 1) begin
				typeCallSys = 16'b0000000000000001;
				pcUp = instPC + 2;
			end
			else if (exceptions[13] == 1) begin
				typeCallSys = 16'b0010000000000000;
				pcUp = instPC + 2;
			end
			else if (exceptions[2] == 1) begin
				typeCallSys = 16'b0000000000000100;
				pcUp = instPC + 2;
			end
			else if (exceptions[3] == 1) begin
				typeCallSys = 16'b0000000000001000;
				pcUp = instPC + 2;
			end
			else if (exceptions[1] == 1) begin
				typeCallSys = 16'b0000000000000010;
				pcUp = instPC + 2;
			end
			else if (exceptions[5] == 1) begin
				typeCallSys = 16'b0000000000100000;
				pcUp = instPC;
				TLBAdress = busAdressWrite;
			end
			else if (exceptions[11] == 1) begin
				typeCallSys = 16'b0000100000000000;
				pcUp = instPC + 2;
			end
			else if (exceptions[12] == 1) begin
				typeCallSys = 16'b0001000000000000;
				pcUp = instPC + 2;
			end
		
		end
		else if (interruption && interrOK) begin
		
			callSys = 1;
			retSys = 0;
			typeCallSys = 16'b1000000000000000;
			pcUp = pc;
		
		end
		else begin
		
			callSys = 0;
			retSys = 0;
			
			if ((busDestinyWrite == 4'b1000) && (busDataWrite[31:28] == 4'b1010) && (busValid == 1)) begin
				readedPcUp = instPC + 2;
				readed = 1;
			end
			
		end
	
	end
	
endmodule

